1. Field of the Invention
The invention relates to an integrated circuit, and more particularly to an integrated circuit comprising an electrostatic discharge (ESD) protection device without lock-on failure.
2. Description of the Related Art
With the advancement of semiconductor manufacturing, protection against electrostatic discharge (ESD) has become one of the most critical reliability issues for integrated circuits (IC). Several ESD test modes, such as machine mode (MM) or human body mode (HBM), have been proposed to imitate the circumstances under which ESD occurs. The ability to withstand certain levels of ESD is essential for successful commercialization of an IC.
ESD protection is also a critical reliability issues for integrated circuits (IC). As semiconductor processes advance toward deep sub-micron manufacturing, resulting scaled-down devices and thinner gate oxides are more vulnerable to ESD stress. Generally, the input/output pads on IC chips must sustain at least 2 kVolt ESD of high stress in HBM or 200V in MM. Thus, the input/output pads on IC chips usually include ESD protection devices or circuits protecting the core circuit from ESD damage.